Model { Name "triggered_r12" Version 4.0 SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off RecordCoverage off CovPath "/" CovSaveName "covdata" CovNameIncrementing off CovHtmlReporting on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon May 26 10:22:08 2003" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Toshi" ModifiedDateFormat "%" LastModifiedDate "Sun Jun 15 05:00:43 2003" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "WorkspaceI/O" LinearizationMsg "none" Profile off AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeLogAll on BufferReuse on SimulationMode "normal" Solver "ode4" SolverMode "Auto" StartTime "0.0" StopTime "inf" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "0.001" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime off TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput off OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "tp004293" Location [329, 313, 838, 620] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType SubSystem Name "sc_console" Ports [2, 1] Position [60, 40, 150, 100] ShowPortLabels on Permissions "ReadWrite" TreatAsAtomicUnit off RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off System { Name "sc_console" Location [187, 116, 665, 353] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "trig_num" Position [15, 83, 45, 97] Port "1" PortDimensions "-1" SampleTime "-1" DataType "auto" SignalType "auto" Interpolate on } Block { BlockType Inport Name "siminfo" Position [15, 118, 45, 132] Port "2" PortDimensions "-1" SampleTime "-1" DataType "auto" SignalType "auto" Interpolate on } Block { BlockType Demux Name "Demux" Ports [1, 2] Position [95, 113, 100, 137] BackgroundColor "black" ShowName off Outputs "[1 3]" BusSelectionMode off } Block { BlockType Reference Name "OpComm" Ports [2, 2] Position [65, 73, 70, 142] SourceBlock "rtlab/OpComm" SourceType "OPAL OpComm Icon" nbport "2" groupe_acq "1" subsys_rate "0" st "0" polling off Synchronization on Interpolation on Threshold "1.0" Missed_Data off Offset off Sim_Time off Samples off dynSigOut off warning_done off writeOpCommFile off from_console "0" } Block { BlockType Scope Name "info" Ports [1] Position [250, 149, 280, 181] Floating off Location [188, 365, 512, 604] Open off NumInputPorts "1" TickLabels "OneTimeTick" ZoomMode "on" List { ListType AxesTitles axes1 "%" } Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType Constant Name "micro-seconds" Position [325, 77, 390, 93] Value "16" VectorParams1D on } Block { BlockType Display Name "overruns" Ports [1] Position [225, 108, 305, 132] Format "short" Decimation "1" Floating off SampleTime "-1" } Block { BlockType Display Name "trigger number" Ports [1] Position [115, 78, 195, 102] Format "short" Decimation "1" Floating off SampleTime "-1" } Block { BlockType Outport Name "delay" Position [425, 78, 455, 92] Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Line { SrcBlock "micro-seconds" SrcPort 1 DstBlock "delay" DstPort 1 } Line { SrcBlock "OpComm" SrcPort 2 DstBlock "Demux" DstPort 1 } Line { SrcBlock "Demux" SrcPort 2 Points [90, 0; 0, 35] DstBlock "info" DstPort 1 } Line { SrcBlock "Demux" SrcPort 1 DstBlock "overruns" DstPort 1 } Line { SrcBlock "OpComm" SrcPort 1 DstBlock "trigger number" DstPort 1 } Line { SrcBlock "trig_num" SrcPort 1 DstBlock "OpComm" DstPort 1 } Line { SrcBlock "siminfo" SrcPort 1 DstBlock "OpComm" DstPort 2 } } } Block { BlockType SubSystem Name "sm_master" Ports [1, 2] Position [210, 40, 320, 100] ShowPortLabels on Permissions "ReadWrite" TreatAsAtomicUnit off RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off System { Name "sm_master" Location [98, 204, 958, 694] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "delay" Position [180, 148, 210, 162] Port "1" PortDimensions "-1" SampleTime "-1" DataType "auto" SignalType "auto" Interpolate on } Block { BlockType Mux Name "Mux" Ports [4, 1] Position [505, 316, 510, 379] ShowName off Inputs "4" DisplayOption "bar" } Block { BlockType Reference Name "Op Subsystem Trigger" Ports [0, 1] Position [25, 23, 155, 57] AncestorBlock "rtlab/Miscellaneous/Op Subsystem Trigger" SourceBlock "rtlab/Miscellaneous/Op Subsystem Trigger" SourceType "Op Subsystem Trigger" nb_subsys "1" Group "1" input off edge "rising edge" } Block { BlockType Reference Name "OpComm" Ports [1, 1] Position [230, 133, 235, 177] SourceBlock "rtlab/OpComm" SourceType "OPAL OpComm Icon" nbport "1" groupe_acq "1" subsys_rate "0" st "0" polling off Synchronization on Interpolation on Threshold "1.0" Missed_Data off Offset off Sim_Time off Samples off dynSigOut off warning_done off writeOpCommFile off from_console "1" } Block { BlockType Reference Name "OpNI-60xE IO Trigger" Ports [] Position [25, 76, 155, 122] SourceBlock "rtlab_io/PCI card/Nationnal Instrument/NI60" "xE/OpNI-60xE IO Trigger" SourceType "Op NI60xE IO Trigger" busType "PCI" cardTypePCI "PCI-6036E" cardTypePXI "PXI-6025E" pciIndex "0" group "1" counter "0" edge "rising edge" active off } Block { BlockType Reference Name "OpSimulationInfo" Ports [1, 4] Position [270, 317, 460, 378] SourceBlock "rtlab/Monitoring/OpSimulationInfo" SourceType "Simulation information" realT off single off timeFactor off overrun on multiRecv off sendFW off calcul on effectSteps on total on cpuSpeed "0" } Block { BlockType SubSystem Name "Triggered\nSubsystem" Ports [1, 1, 0, 1] Position [275, 90, 520, 220] ShowPortLabels on Permissions "ReadWrite" TreatAsAtomicUnit on RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off System { Name "Triggered\nSubsystem" Location [84, 116, 689, 601] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "delay" Position [140, 138, 170, 152] Port "1" PortDimensions "-1" SampleTime "-1" DataType "auto" SignalType "auto" Interpolate on } Block { BlockType TriggerPort Name "Trigger" Ports [] Position [290, 15, 310, 35] TriggerType "function-call" ShowOutputPort off OutputDataType "auto" } Block { BlockType Constant Name "Constant" Position [200, 235, 220, 255] ShowName off Value "1" VectorParams1D on } Block { BlockType Ground Name "Ground" Position [190, 160, 210, 180] } Block { BlockType Memory Name "Memory" Position [280, 275, 300, 295] Orientation "left" X0 "0" InheritSampleTime off } Block { BlockType Reference Name "OpDelay" Ports [2, 1] Position [235, 131, 385, 184] AncestorBlock "rtlab/Monitoring/OpDelay" SourceBlock "rtlab/Monitoring/OpDelay" SourceType "OPAL Delay Icon" option "1" synchro off } Block { BlockType Sum Name "Sum" Ports [2, 1] Position [255, 235, 275, 255] ShowName off IconShape "round" Inputs "|++" SaturateOnIntegerOverflow on } Block { BlockType Terminator Name "Terminator" Position [410, 150, 430, 170] } Block { BlockType Outport Name "trig_num" Position [335, 238, 365, 252] Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Line { SrcBlock "Ground" SrcPort 1 DstBlock "OpDelay" DstPort 2 } Line { SrcBlock "delay" SrcPort 1 DstBlock "OpDelay" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Sum" SrcPort 1 Points [0, 0; 35, 0] Branch { DstBlock "trig_num" DstPort 1 } Branch { DstBlock "Memory" DstPort 1 } } Line { SrcBlock "Memory" SrcPort 1 Points [-10, 0] DstBlock "Sum" DstPort 2 } Line { SrcBlock "OpDelay" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType Outport Name "trig_num" Position [555, 148, 585, 162] Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Outport Name "siminfo" Position [550, 343, 580, 357] Port "2" OutputWhenDisabled "held" InitialOutput "[]" } Line { SrcBlock "Op Subsystem Trigger" SrcPort 1 Points [235, 0] DstBlock "Triggered\nSubsystem" DstPort trigger } Line { SrcBlock "delay" SrcPort 1 DstBlock "OpComm" DstPort 1 } Line { SrcBlock "Triggered\nSubsystem" SrcPort 1 DstBlock "trig_num" DstPort 1 } Line { SrcBlock "OpComm" SrcPort 1 DstBlock "Triggered\nSubsystem" DstPort 1 } Line { SrcBlock "OpSimulationInfo" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "OpSimulationInfo" SrcPort 2 DstBlock "Mux" DstPort 2 } Line { SrcBlock "OpSimulationInfo" SrcPort 3 DstBlock "Mux" DstPort 3 } Line { SrcBlock "OpSimulationInfo" SrcPort 4 DstBlock "Mux" DstPort 4 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "siminfo" DstPort 1 } } } Line { SrcBlock "sc_console" SrcPort 1 DstBlock "sm_master" DstPort 1 } Line { SrcBlock "sm_master" SrcPort 1 Points [5, 0; 0, 70; -290, 0; 0, -70] DstBlock "sc_console" DstPort 1 } Line { SrcBlock "sm_master" SrcPort 2 Points [0, 35; -280, 0] DstBlock "sc_console" DstPort 2 } } }