Model { Name "var_change_r12" Version 5.1 SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovNameIncrementing off CovHtmlReporting on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off PreLoadFcn "Var = 1;" InitFcn "Var = 1;" Created "Tue May 25 17:03:44 2004" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Toshi" ModifiedDateFormat "%" LastModifiedDate "Tue May 25 18:37:02 2004" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeLogAll on BufferReuse on SimulationMode "normal" Solver "FixedStepDiscrete" SolverMode "Auto" StartTime "0.0" StopTime "inf" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "0.1" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "tp370058" Location [118, 82, 698, 375] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType SubSystem Name "SC_Console" Ports [1] Position [240, 80, 280, 140] ShowPortLabels on Permissions "ReadWrite" TreatAsAtomicUnit off RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off System { Name "SC_Console" Location [257, 323, 567, 417] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType Inport Name "In1" Position [25, 43, 55, 57] Port "1" PortDimensions "-1" SampleTime "-1" DataType "auto" SignalType "auto" Interpolate on } Block { BlockType Display Name "Display" Ports [1] Position [195, 35, 285, 65] Format "short" Decimation "1" Floating off SampleTime "-1" } Block { BlockType Reference Name "OpComm" Ports [1, 1] Position [80, 29, 115, 71] SourceBlock "rtlab/OpComm" SourceType "OPAL OpComm Icon" nbport "1" groupe_acq "1" subsys_rate "0" st "0" polling off Synchronization on Interpolation on Threshold "1.0" Missed_Data off Offset off Sim_Time off Samples off dynSigOut off warning_done off writeOpCommFile off from_console "0" } Line { SrcBlock "OpComm" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 DstBlock "OpComm" DstPort 1 } } } Block { BlockType SubSystem Name "SM_Master" Ports [0, 1] Position [125, 80, 165, 140] ShowPortLabels on Permissions "ReadWrite" TreatAsAtomicUnit off RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off System { Name "SM_Master" Location [97, 348, 232, 430] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType Constant Name "Constant" Position [25, 25, 55, 55] Value "Var" VectorParams1D on } Block { BlockType Outport Name "Out1" Position [80, 33, 110, 47] Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Line { SrcBlock "SM_Master" SrcPort 1 DstBlock "SC_Console" DstPort 1 } } }